// module name: MUXs
// author: yangtao2019
// date: 2021.07.11

`timescale 1ns / 1ps

module two2oneMUX
(
    input code,
    input[63:0] data_in0,
    input[63:0] data_in1,
    output[63:0] data_out
);

    assign data_out =   (code==1'b0) ?  data_in0:
                        (code==1'b1) ?  data_in1:
                                        63'b0; 

endmodule


module four2twoMUX
(
    input[1:0]  code,
    input[63:0] data_in0,
    input[63:0] data_in1,
    input[63:0] data_in2,
    input[63:0] data_in3,
    output[63:0] data_out
);

    assign data_out =   (code==2'd0) ?  data_in0:
                        (code==2'd1) ?  data_in1:
                        (code==2'd2) ?  data_in2:
                        (code==2'd3) ?  data_in3:
                                        63'b0; 

endmodule


